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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Quad Bus Receiver
The MC10129 data inputs are compatible with, and accept TTL logic levels as well as levels compatible with IBM-type buses. The clock, strobe, and reset inputs accept MECL 10,000 logic levels. The data inputs accept the bus levels, and storage elements are provided to yield temporary latch storage of the information after receiving it from the bus. The outputs can be strobed to allow accurate synchronization of signals and/or connection to MECL 10,000 level buses. When the clock is low, and the reset input is disabled, the outputs will follow the D inputs. The latches will store the data on the rising edge of the clock. The outputs are enabled when the strobe input is high. Unused D inputs must be tied to VCC or Gnd. The clock, strobe, and reset inputs each have 50 k ohm pulldown resistors to VEE. They may be left floating, if not used. The MC10129 will operate in either of two modes. The first mode is obtained by tying the hysteresis control input to VEE. In this mode, the input threshold points of the D inputs are fixed. The second mode is obtained by tying the hysteresis control input to ground. In this mode, input hysteresis is achieved as shown in the test table. This hysteresis is desirable where extra noise margin is required on the D inputs. The outer input pins are unaffected by the mode of operation used. The MC10129 is especially useful in interface applications for central processors, mini-computers, and peripheral equipment. PD = 750 mW typ/pkg (No Load) tpd = 10 ns typ VCC Max = 7.0 Vdc
MC10129
L SUFFIX CERAMIC PACKAGE CASE 620-10
PIN ASSIGNMENT
GND Q3 Q2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 GND Q1 Q0 D1 STROBE CLOCK RESET VCC
LOGIC DIAGRAM
D0 7 D C R
D3 HYSTERESIS CONTROL 14 Q0 D2 D0 VEE
D1 13
D C R
15 Q1
D2 6
D C R
3 Q2
TRUTH TABLE
D C X H L H L STROBE L X H H H RESET X H X L X Qn + 1 L L L Qn H 2 Q3 X X L X H
D3 4 HYSTERESIS CONTROL CLOCK RESET STROBE
D C R VCC = PIN 9 GND = PIN 1 AND 16 VEE = PIN 8
5 11 10 12
9/96
(c) Motorola, Inc. 1996
3-1
REV 6
MC10129
ELECTRICAL CHARACTERISTICS
Test Limits Pin Under Test 8 8 9 4 6 7 10 11 12 13 4 6 7 13 10 11 12 2 3 2 3 2 3 2 3 2 (2.) 2 2 2 2 (3.) 2 (4.) 2 2 2 2 2 2
(2.) (2.) (3.) (4.)
-30C Min Max 167 189 8.0 150 150 150 720 390 390 150 1.5 1.5 1.5 -1.0 0.5 0.5 0.5 -1.060 -1.060 -1.060 -1.060 -1.890 -1.890 -1.890 -1.890 -1.080 -1.080 -1.080 -1.080 -1.080 -1.080 -1.655 -1.655 -1.655 -1.655 -1.655 -1.655 -0.890 -0.890 -0.890 -0.890 -1.675 -1.675 -1.675 -1.675 0.5 0.5 0.5 -0.960 -0.960 -0.960 -0.960 -1.850 -1.850 -1.850 -1.850 -0.980 -0.980 -0.980 -0.980 -0.980 -0.980 Min
+25C Typ Max 152 172 8.0 95 95 95 450 245 245 95 -1.0 -1.0 -1.0 0.3 0.3 0.3 -0.810 -0.810 -0.810 -0.810 -1.650 -1.650 -1.650 -1.650 Min
+85C Max 167 189 8.0 95 95 95 450 245 245 95 1.0 1.0 1.0 Unit mAdc mAdc Adc
Characteristic Negative Power Supply Drain Current Positive Power Supply Drain Current Input Current
Symbol IE ICC IinH
ICBO (1.)
Adc
IinL
Adc
Output Voltage
Logic 1
VOH
-0.890 -0.890 -0.890 -0.890 -1.825 -1.825 -1.825 -1.825 -0.910 -0.910 -0.910 -0.910 -0.910 -0.910
-0.700 -0.700 -0.700 -0.700 -1.615 -1.615 -1.615 -1.615
Vdc
Output Voltage
Logic 0
VOL
Vdc
Threshold Voltage
Logic 1
VOHA
Vdc
Threshold Voltage
Logic 0
VOLA
-1.630 -1.630 -1.630 -1.630 -1.630 -1.630
-1.595 -1.595 -1.595 -1.595 -1.595 -1.595
Vdc
Switching Times Propagation Delay Data Input Clock Input Strobe Input Reset Input Hysteresis Mode Setup Time Hold Time Rise Time Fall Time t7+14+ t7-14- t11-14+ t11-14- t12+14+ t12-14- t10+14- t7+14+ t7-14- tsetup thold t+ t- 14 14 14 14 14 14 14 14 14 14 14 14 14 3.7 3.7 2.7 2.7 1.6 1.6 2.0 6.6 3.7 30 0 1.5 1.5 5.0 5.0 15 15 11 11 8.0 8.0 8.0 30 17 3.7 3.7 2.7 2.7 1.6 1.6 2.0 6.7 3.7 2.7 -2.0 1.5 1.5 10 10 5.0 5.0 4.0 4.0 5.0 18 10 15 15 2.0 2.0 4.3 4.3 15 15 9.0 9.0 7.0 7.0 6.5 25 15 3.7 3.7 2.7 2.7 1.6 1.6 2.0 6.6 3.7 30 -2.0 1.5 1.5 5.0 5.0 30 40 11 11 8.0 8.0 8.0 30 40
ns
1. Pin 5 to VEE, VIL to Data input one at a time. 2. Output latched to logic high state prior to test. VIHA, VILA are standard logic 1 and logic 0 MTTL threshold voltages. VIHA, VILA, VIHA and VILA are logic 1 and logic 0 threshold voltages in the hysteresis mode as shown in Figure 1 on page 3-2. 3. Input level on data input taken from +0.4V up to voltage level given. 4. Input level on data input taken from +4.0V down to voltage level given. 5. Operation and limits shown also apply for VCC = +6.0V.
VIHA
VIHA
Hysteresis Mode Threshold Voltage
Logic 1 Vout Logic 0 VILA VILA Vin
Figure 1. Hysteresis Mode Threshold Voltage
MOTOROLA
3-2
MECL Data DL122 -- Rev 6
MC10129
ELECTRICAL CHARACTERISTICS
TEST VOLTAGE VALUES (Volts) MECL 10,000 INPUT LEVELS @ Test Temperature -30C +25C +85C Pin Under Test 8 8 9 4 6 7 10 11 12 13 4 6 7 13 10 11 12 2 3 2 3 2 3 2 3 2 (2.) 2 2 2 2 (3.) 2 (4.) 2 2 2 2 2 2
(2.) (2.) (3.) (4.)
TTL INPUT LEVELS (6.) VIH 3.000 3.000 3.000 VIL 0.400 0.400 0.400 VIHA 2.000 2.000 2.000 VILA 0.800 0.800 0.800
VIHmax -0.890 -0.810 -0.700
VILmin -1.890 -1.850 -1.825
VIHAmin -1.155 -1.105 -1.035
VILAmax -1.500 -1.475 -1.440
TEST VOLTAGE APPLIED TO PINS LISTED BELOW VIHmax 11 11 VILmin 12 12 4,6,7,13 4 6 7 10,11 11 12 13 4 6 7 13 10 11 12 12 12 12 12 12 12 12 12 11,12 10,11 10,12 12 12 12 11,12 10,11 10,12 12 12 12 +1.11V 11 10,11 10,11 10,11 +0.31V 10,11 10,11 10 10 10,11 10,11 12 12 12 12 12 12 12 10,11 10,11 10 10 10,11 10,11 Pulse In 7 7 7,11 7,11 12 12 10,11 7 7 7,11 7,11 7 7 Pulse Out 14 14 14 14 14 14 14 14 14 14 14 14 14 7 7 7 7 +5.0V +2.40V Figure Figure 3 Figure 3 Figure 6 Figure 6 Figure 4 Figure 4 Figure 5 Figure 3 Figure 3 Figure 7 Figure 7 Figure 3 Figure 3 10,11 10,11 10,11 10 12 4 4 4 4 12 11 10,11 10,11 10,11 10,11 10,11 10,11 10,11 10,11 10 4 4 4 4 4 6 4 6 4 6 4 6 VIHAmin VILAmax VIH VIL VIHA VILA Gnd 1,5,16 1,16 1,16 1,16 1,16 1,16 1,16 1,16 1,16 1,16 1,16 1,16 1,16 1,16 1,16 1,16 1,16 1,16 1,16 1,5,16 1,5,16 1,16 1,16 1,5,16 1,5,16 1,16 1,16 1,16 1,16 1,5,16 1,5,16 1,16 1,16 1,16 1,16 1,5,16 1,5,16 +2.0V 1,16 1,16 1,16 1,16 1,16 1,16 1,16 1,5,16 1,5,16 1,16 1,16 1,16 1,16
Characteristic Negative Power Supply Drain Current Positive Power Supply Drain Current Input Current
Symbol IE ICC IinH
ICBO (1.)
IinL
Output Voltage Logic 1
VOH
Output Voltage Logic 0
VOL
Threshold Voltage Logic 1
VOHA
Threshold Voltage Logic 0
VOLA
Switching Times Propagation Delay Data Input Clock Input Strobe Input Reset Input Hysteresis Mode Setup Time Hold Time Rise Time Fall Time t7+14+ t7-14- t11-14+ t11-14- t12+14+ t12-14- t10+14- t7+14+ t7-14- tsetup thold t+ t- 14 14 14 14 14 14 14 14 14 14 14 14 14
12 12 12 12
1. Pin 5 to VEE, VIL to Data input one at a time. 2. Output latched to logic high state prior to test. VIHA, VILA are standard logic 1 and logic 0 MTTL threshold voltages. VIHA, VILA, VIHA and VILA are logic 1 and logic 0 threshold voltages in the hysteresis mode as shown in Figure 1 on page 3-2. 3. Input level on data input taken from +0.4V up to voltage level given. 4. Input level on data input taken from +4.0V down to voltage level given. 5. Operation and limits shown also apply for VCC = +6.0V. 6. When testing, choose either TTL or IBM input levels.
MECL Data DL122 -- Rev 6
3-3
MOTOROLA
MC10129
ELECTRICAL CHARACTERISTICS
TEST VOLTAGE VALUES (Volts) IBM INPUT LEVELS (6.) @ Test Temperature -30C +25C +85C Pin Under Test 8 8 9 4 6 7 10 11 12 13 4 6 7 13 10 11 12 2 3 2 3 2 3 2 3 2 (2.) 2 2 2 2 (3.) 2 (4.) 2 2 2 2 2 2
(2.) (2.) (3.) (4.)
HYSTERESIS MODE VIHA 2.90 2.60 2.30 VILA 2.00 1.70 1.40 VIHA 2.20 1.90 1.60 VILA 1.30 1.00 0.70 VCC (5.) +5.0 +5.0 +5.0 VEE -5.2 -5.2 -5.2
VIH 3.11 3.11 3.11
VIL 0.150 0.150 0.150
VIHA 1.700
VILA 0.70
TEST VOLTAGE APPLIED TO PINS LISTED BELOW VIH VIL VIHA VILA VIHA VILA VIHA VILA VCC (5.) 9 9 4,6, 7,13 4 6 7 9 9 9 9 9 9 9 9 9 4 6 7 13 9 9 9 9 9 9 9 4 6 4 6 4 6 4 6 4 4 4 4 4 4 4 4 4 4 4 4 +5.0V +2.40V Figure Figure 3 Figure 3 Figure 6 Figure 6 7 7 7 Figure 4 Figure 4 Figure 5 Figure 3 Figure 3 Figure 7 Figure 7 Figure 3 Figure 3 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 +7.0V 9 9 9 9 9 9 9 9 9 9 9 9 9 VEE 8 5,8 5,8 5,8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 5,8 5,8 8 8 5,8 5,8 8 8 5,8 5,8 5,8 5,8 8 8 5,8 5,8 5,8 5,8 8 8 -3.2V 5,8 5,8 5,8 5,8 5,8 5,8 5,8 8 8 5,8 5,8 5,8 5,8 Gnd 1,5,16 1,16 1,16 1,16 1,16 1,16 1,16 1,16 1,16 1,16 1,16 1,16 1,16 1,16 1,16 1,16 1,16 1,16 1,16 1,16 1,5,16 1,5,16 1,16 1,16 1,5,16 1,5,16 1,16 1,16 1,16 1,16 1,5,16 1,5,16 1,16 1,16 1,16 1,16 1,5,16 1,5,16 +2.0V 1,16 1,16 1,16 1,16 1,16 1,16 1,16 1,5,16 1,5,16 1,16 1,16 1,16 1,16
Characteristic Negative Power Supply Drain Current Positive Power Supply Drain Current Input Current
Symbol IE ICC IinH
13
ICBO (1.)
IinL
Output Voltage Logic 1
VOH
Output Voltage Logic 0
VOL
Threshold Voltage Logic 1
VOHA
Threshold Voltage Logic 0
VOLA
Switching Times Propagation Delay Data Input Clock Input Strobe Input Reset Input Hysteresis Mode Setup Time Hold Time Rise Time Fall Time t7+14+ t7-14- t11-14+ t11-14- t12+14+ t12-14- t10+14- t7+14+ t7-14- tsetup thold t+ t- 14 14 14 14 14 14 14 14 14 14 14 14 14
1. Pin 5 to VEE, VIL to Data input one at a time. 2. Output latched to logic high state prior to test. VIHA, VILA are standard logic 1 and logic 0 MTTL threshold voltages. VIHA, VILA, VIHA and VILA are logic 1 and logic 0 threshold voltages in the hysteresis mode as shown in Figure 1 on page 3-2. 3. Input level on data input taken from +0.4V up to voltage level given. 4. Input level on data input taken from +4.0V down to voltage level given. 5. Operation and limits shown also apply for VCC = +6.0V. 6. When testing, choose either TTL or IBM input levels.
MOTOROLA
3-4
MECL Data DL122 -- Rev 6
MC10129
Figure 2. SWITCHING TIME TEST CIRCUIT AND WAVEFORMS @ 25C
VCC +7.0 Vdc 25 F 0.1 F Vout
Vin
+5.0 Vdc
Coax
0.1 F
Coax
7 D0 Input CR Pulse Generator Input Pulse t+ = t- = 5.5 0.5 ns (10 to 90%) Unused Inputs (D) must be tied to VCC or Pin 16 6 50-ohm termination to ground located in each scope channel input. All input and output cables to the scope are equal lengths of 50-ohm coaxial cable. Wire length should be < 1/4 inch from TPin to input pin and TPout to output pin. Hysteresis Control Clock Reset Strobe D2 D CR 13 D1 D C R D
14 Q0
15 Q1
3 Q2
Unused outputs connected to a 50-ohm resistor to ground.
4 D3 D C 5 11 10 12 R
2 Q3
1 16 25 F
8 0.1 F
+ 2.0 Vdc
-3.2 Vdc VEE
NOTE: All power supplies and logic levels are shifted 2 volts positive.
MECL Data DL122 -- Rev 6
3-5
MOTOROLA
MC10129
Figure 3 - DATA to OUTPUT (Clock and Reset are low, Strobe is high)
+5.0 V 50% Data t+ t- +2.4 V
Figure 4 - STROBE to OUTPUT (Data is high, Clock and Reset are low)
+1.11 V Strobe 50% +0.31 V t+ t-
Q
80% 50% 20%
+1.11 V +0.31 V Q 80% 50% 20%
+1.11 V +0.31 V
t7+14+
t7-14-
t12+14+
t12-14-
Figure 6 - CLOCK to OUTPUT (Reset is low, Strobe is high)
Data +5.0 V +2.4 V Clock +1.11 V 50% Q Reset +0.31 V 50% t- 50% t+ 80% 50% 20% +0.31 V +1.11 V +0.31 V +1.11 V
Figure 5 - RESET to OUTPUT (Data and Strobe are high)
Clock 50%
+1.11 V t11-14- +0.31 V t+ t- t11-14+
Figure 7 - TSET UP AND THOLD WAVEFORMS
80% 50% Q 20% +1.11 V 50% D +0.31 V tsetup 50% C t11-14+ +0.31 V thold 50% +2.400 V +1.11 V +5.00 V
t10+14-
Q
MOTOROLA
3-6
MECL Data DL122 -- Rev 6
MC10129
OUTLINE DIMENSIONS
L SUFFIX CERAMIC DIP PACKAGE CASE 620-10 ISSUE V
9
-A-
16
-B-
1 8
C
L
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. DIM A B C D E F G H K L M N INCHES MIN MAX 0.750 0.785 0.240 0.295 --- 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 --- 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01
-T-
SEATING PLANE
N E F D G
16 PL
K M J
16 PL
0.25 (0.010)
M
M
TB
S
0.25 (0.010)
TA
S
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JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 81-3-3521-8315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298
MECL Data DL122 -- Rev 6 3-7
*MC10129/D*
MC10129/D MOTOROLA

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